1. Field of the Invention
The present invention relates to a pre-fetch control apparatus for use in an information processing apparatus comprising cache memory.
2. Description of the Related Art
A high-speed access to memory has been conventionally devised by providing cache memory between a central processing unit (CPU) and a main storage apparatus. In recent years, the time required for a memory access to access a main storage apparatus has become large compared to the increased speed of the instruction execution cycle of a CPU, requiring further improvements in the hit ratio of cache memory and in cache miss latency. A method called a pre-fetch has been used as one countermeasure to such a problem. The pre-fetch is used for lowering a cache miss ratio by pre-reading, in cache memory, an instruction or data that will be needed in the near future.
There is, however, a possibility of expelling necessary data from the cache if extraneous data is pre-fetched, possibly resulting in increasing the cache miss ratio. Because of this, an important problem to be solved is how the address of data to be pre-fetched is to be predicted. For example, reference patent document 1 has proposed a method for finding out an address in which continuous lines have been accessed in the past by registering a cache-accessed address in an access queue and for obtaining a pre-fetch address on the basis of the found address, thereby preventing extraneous pre-fetches.
In the conventional technique, however, there have been cases in which an entry or entries overflow from a pre-fetch address queue if there is a series of memory accesses exceeding the number of entries of the aforementioned queue, resulting in a malfunction of the pre-fetch.
Patent document 1: Laid-Open Japanese Patent Application Publication No. 2004-38345